Semiconductor packages house and protect semiconductor devices from the external environment of the package, and provide electrical connection from the semiconductor devices to the exterior of the package. One of the most widely adopted methods for electrical connection between the semiconductor die and the semiconductor package that encapsulates the die is through bondwire assembly (also known as wire bonding).
The diagram show in FIG. 1 is typically referred to in the industry as a ‘bonding diagram’. It is essentially an overlay of the top view of IC die and package, with straight lines depicting the bondwires that electrically connect the IC with the package. Bonding diagrams are the usual means of communication between IC package designers and assembly houses which provide wire bonding services. The information contained in a bonding diagram is in two dimensions and is sufficient to define IC and package connectivity, but is not sufficient for enabling electromagnetic modelling of bondwires.
The wide use of bondwires is mainly attributed to the fact that they are a versatile and low-cost assembly option for a wide range of integrated circuit (IC) packages. However, in high-speed and high-frequency IC design, bondwires introduce parasitics such as inductance and magnetic coupling which may affect product performance significantly. To meet demanding product specifications and time-to-market requirements, IC designers need the ability to easily draw, model and optimize bondwire as part of circuit design. Therefore, the existence of an Electronic Design Automation (EDA) tool that allows the rapid and accurate modelling of the electromagnetic behaviour of bondwires is vital to ensure that the combination of semiconductor die and package will meet required specifications.
However, most EDA tools found in the prior art are focused on integrated circuit design. Several tools and methodologies have been developed in the past that allow the fast and accurate modelling of metallic interconnects belonging to a semiconductor die layout. Some of these methodologies are based on equivalent circuit extraction. In such methodologies, the interconnect structures of the integrated circuit are divided into smaller sections, and each section is modelled by an equivalent circuit that models its electromagnetic behaviour, including electrical behaviour, along with any parasitic couplings to the substrate or other nearby structures. The aforementioned methodologies are usually fast and efficient. Their output is usually a circuit netlist comprising R (resistor) and C (capacitor) lumped elements. Commercial EDA tools such as Diva® and Assura® RCX of Cadence and Calibre® xRC of Mentor Graphics fall under this category. Some methods are also capable of producing L (inductance) and K (mutual inductance) elements, which besides R, C are required to accurately model the EM behaviour at higher frequencies. Commercial FDA tools that fall under the latter category include VeloceRF™ of Helic. However, even though bondwires may conceptually be considered as an extension of the metallic interconnects on an IC die, none of the aforementioned commercial tools and related methodologies in the prior art are applicable to the modelling of bondwires.
It is known in electromagnetic (EM) modelling of packages (including bondwires), for design and test engineers to use simulator tools, known as EM solvers, that employ numerical electromagnetic modelling methodologies. These tools are invariably based on Maxwell's equations, and attempt to solve them using various known numerical techniques such as Method of Moments {MoM), Finite Elements Method (FEM), Finite Differences Time Domain (FDTD). The main advantage of these methods is their wide applicability as they are able to generate models for complex three-dimensional (3D) geometries that comprise a semiconductor package. Commercial EM solvers include HFSS® of Ansoft and Momentum® of Agilent Technologies.
However, a disadvantage of such numerical methods is that they are extremely time and memory consuming. The effective description of the EM fields requires equations that cannot be solved analytically and require numerical solutions which often generate very large matrices and employ iterative procedures that may be slow to converge to a solution. Due to the complexity of a typical semiconductor package, often comprising large numbers of pins and multiple levels of interconnects, simulation time for a single package can last several hours or even days. Given the time taken to model the EM fields of bondwires, it is desirable to be able to model these fields in a more efficient manner with minimal loss in the accuracy or the model.
An additional drawback of known EM solvers is the lack of integration between package and integrated circuit design. As discussed previously, most IC design tools utilize equivalent circuits that are simulated by electronic circuit simulators (such as SPICE). On the other hand, most package design tools use numerical electromagnetic tools that yield the results in the form of network parameters, making integration and co-simulation with the die difficult. An attempt to solve these drawbacks was the introduction of the Partial Element Equivalent Circuit (PEEC) method. This method discretizes the electromagnetic problem to a vast array of equivalent circuit elements, and can be applied for the modelling of multilayered die and package substrates. Even though it manages to relate the electromagnetic problem to a circuit implementation, it does so at the cost of generating large and complex netlists that often lead to a prohibitively high computing cost (in terms of both time and memory) for simulation. It is therefore desirable to be able to integrate the IC and EM modelling in order to reduce computational costs and to improve efficiency when designing circuits that incorporate bondwires.
Several modifications have been proposed in the past to improve the methodologies used for package simulation, and overcome some of their major drawbacks. US patent 20050251378 claims a method that is based on a modification of the PEEC methodology, allowing the discretization of only the metallization instead of the whole structure, thus improving the overall performance of the method. In U.S. Pat. No. 5,694,344, a method is claimed for electrically modelling planar interconnects in a semiconductor package; this method is in accordance with techniques implemented in IC layout extraction tools.
However, the aforementioned improvements take advantage of the multi-layer nature of the semiconductor die or package, comprising wirings extending on multiple planar layers, with vertical interconnects providing connectivity between them. This specific layered structure of integrated circuits and package substrates, known as 2.5 dimensional space, allows the utilization of such techniques that enhance the performance of the method applied. When it comes to the modelling of bondwire interconnects, such methodologies cannot be applied. Bondwires have complex 3D shapes extending in all directions in three-dimensional (3D) space. Furthermore, their shape varies and unlike the metallization in layered media, they do not follow regular geometric patterns and therefore these inventions are unable to solve the problems in the modelling of bondwires mentioned above.
In this respect, when it comes to bondwire modelling with the prior art designers utilise EM solvers that make use of one of the aforementioned general-purpose numerical techniques. Since most modern IC packages offer high pin counts with resultantly large scales of integration, the amount and complexity of the bondwire interconnects is in most cases too great to be effectively handled by the existing tools.
Therefore, a system and method that could offer accurate modelling of bondwire interconnects in a short amount of time, and produce models that can easily be co-simulated with integrated circuit netlists, would be of great benefit to IC designers over the prior art.
Accordingly some known deficiencies in the prior art are that the prior art is currently unable to:                1. Define and model bondwire interconnects in the same environment that is used for IC circuit design and layout extraction, without the need for external tools.        2. Model bondwire interconnects in three dimensions, using methodologies of similar nature to the well-known techniques used in the extraction of IC layouts, techniques that are faster and more efficient than conventional EM solvers.        